References available.

Urban School of San Francisco    (urbanschool.org) San Francisco, CA (11/16 - 06/17)

Interim Mathematics Teacher :  Functions, Math 3B, Math1A, and Math2A    (Course Descriptions)

Lisa Kampner Hebrew Academy    (hebrewacademy.com) San Francisco, CA (08/12 - 07/16)   Reference Letter

Mathematics Teacher :  Algebra 1,  Geometry,  Algebra 2,  Precalculus,  and AP Calculus AB

Director of Educational Technology,   Webmaster   (hebrewacademy.com/RajMangewala)

Accomplishments:

  • Engaged and completely supported students on a daily basis in the pursuit of learning and retaining high level mathmatics.
  • Developed common core aligned curriculum and lessons for all high school math classes taught.
  • AP Calculus AB pass rate above 60%. The pass rate for years previous was below 15%.
  • Started, facilitated, and maintained a yearly summer Math SAT workshop program.
  • Created an informal lunch tutoring space by opening classroom early everyday and volunteering time.
  • Implemented school wide Google Apps for Education integration.
  • Integrated Khan Academy interactive problem sets into math lessons.
  • Designed/developed an online grade submission and automated report card generation protocol leveraging Google Apps.
  • Completed fundraising effort software project by converting the ICJME.com mail order catalog to an online digital download format.
  • Maintained and administered online gradebook accounts for staff as needed.

Chinese American International School San Francisco, CA (05/09 - 06/11) Assistant Teacher

  • Worked with multicultural population of K-8 students. Assisted teachers with in class support of students as well as lesson planning and leading.

Burton High School San Francisco, CA (8/06 - 8/07) Mathematics Teacher.

  • Worked with at-risk high school students as a full time math teacher, including lesson planning and assesment of individual needs.

Galileo High School San Francisco, CA (9/05 - 6/06) Student Teacher.

  • As a student teacher I observed and worked under master teachers developing both management and lesson planning skills.

UC Santa Barbara Tutorial Center (9/95 - 3/96) Calculus/Physics Tutor.

  • Tutored undergraduate students in Math and Physics.

Short Term

  • Front end web developer for Amazon subsidiary company, Alexa Internet.
  • Responsible engineer for full stack implementation of commercial website for a Real Estate business. This project includes a custom CMS for properties and clients. Also responsible for installation and bring-up of development web server(Apache).

Open Source

  • Responsible engineer for full stack implementation of SignedWars, an educational application.

Entrepreneurial

  • Responsible engineer for full stack implementation of SchoolAdmin SaaS application.

A significant portion of the ASIC development cycle involves writing object oriented code representing the hardware devices to be manufactured. I have been the responsible engineer for the full chip code base on multiple projects.


Almaden Technology (10 person start-up) Sunnyvale, CA. (5/03 - 6/04) Senior Design Engineer

  • Architected and implemented traffic shaping logic for a switch chip deployed in MAN system by Nokia Siemens.
  • Architected and implemented 32-bit PCI local Bus.
  • Developed block synthesis, static timing, and scan insertion Synopsys scripts for entire design.

ICPlus Corporation Hsin-Chu, Taiwan. (2/03 - 4/03) Contract ASIC Design Engineer

  • Architected and implemented 125MHz AMBA AHB bussing protocol associated with ARM RISC microcontroller and integrated with existing DMA to ethernet Media Access Controller to be incorporated into home gateway SoC design. Also developed block synthesis, static timing, and scan insertion Synopsys scripts for new design.
  • Re-architected existing datapath and embedded RAM structure to yield smaller die size and reduce overall system cost.
  • Worked with team of engineers in Taiwan to determine block signaling interface and timing budgets. Helped with FPGA prototyping and system integration.

Sundance Technology (6 person start-up) San Jose, CA. (1/98 - 1/03) Senior Design Engineer

  • Devised and implemented chip synthesis, static timing, and scan methodologies for design team creating PCI to 10/100/1000 Mbps Ethernet Media Access Controller with and without integrated PHY.
  • Architected, implemented and tested the following functional blocks: 64-bit/66MHz PCI Local Bus, 64-bit/133MHz PCI-X Local Bus, PCI Power Management logic, Buffer management logic incorporating 1 single port RAM providing bandwidth to both transmit and receive datapaths, Card Bus Interface, ROM and EEPROM chip level interfaces, register file.
  • Performed FPGA prototyping, system integration, customer support, compliance testing.
  • Worked with engineers from partners company as part of a Joint venture to create a 10/100 integrated MAC + PHY.
  • Developed company wide rtl coding guidelines and synthesis scripting templates. Trained new employees in all aspects of ASIC design including coding styles, sythesis and timing considerations, design for test, block and system level integration.

Cypress Semiconductor San Jose, CA. (3/96 - 12/97) Design Engineer

  • Part of a team designing 10/100 Mbps Ethernet PHY Transceiver. Architected, implemented and maintained digital portion of 10/100 Mbps Ethernet Tx PHY Transceiver.
  • Developed and implemented Verilog HDL code for digital portion of 10/100 PHY. Also wrote Verilog and scripts for full chip synthesis, static timing using Synopsys tools. Trained other engineers in using these flows & toolsets.
  • Developed and implemented full scan test strategies using Synopsys tools.

Amdahl Corporation Sunnyvale, CA. (7/92 - 7/93) Associate Design Engineer

  • Member of logic design team developing a Bi-Polar technology chips for a mainframe computer. Specific responsibilities included logic design/entry, physical placement, timing analysis, and simulation of the addressing unit for the CPU.
  • Volunteered to be part of an early team investigating HDL code and Synopsys synthesis tools for high-level simulation of the next generation CPU for a CMOS based mainframe computer.